Integrated circuits are the cornerstone of the information age and the foundation of today's information technology industry. The integrated circuit, a.k.a. “chip” or “microchip,” is a set of interconnected electronic components, such as transistors, capacitors, and resistors, which are etched or imprinted onto a tiny wafer of semiconducting material, such as silicon or germanium. Integrated circuits take on various forms including, as some non-limiting examples, microprocessors, amplifiers, Flash memories, application specific integrated circuits (ASICs), static random access memories (SRAMs), digital signal processors (DSPs), dynamic random access memories (DRAMs), erasable programmable read only memories (EPROMs), electrically erasable programmable read only memories (EEPROMs), and programmable logic. Integrated circuits are used in innumerable products, including personal, laptop and tablet computers, consumer electronics, such as smartphones and flats-screen televisions, medical instruments, telecommunication and networking equipment, airplanes, and automobiles.
Advances in integrated circuit (IC) technology and microchip manufacturing have led to a steady decrease in chip size and an increase in circuit density and circuit performance. Modern day integrated circuits, while small enough to fit in the hand of child, have millions of devices, including logic gates and transistors, and a very complex photolithographic layout. The scale of semiconductor integration has advanced to the point where a single semiconductor chip can hold tens of millions to over a billion devices in a space smaller than a U.S. penny. Moreover, the width of each conducting line in a modern microchip can be made as small as a fraction of a nanometer. The operating speed and overall performance of a semiconductor chip (e.g., clock speed and signal net switching speeds) has concomitantly increased with the level of integration. To keep pace with increases in on-chip circuit switching frequency and circuit density, semiconductor packages currently offer higher pin counts, greater power dissipation, more protection, and higher speeds than packages of just a few years ago.
A variety of specialized software tools have been developed to meet the challenges of designing and manufacturing more complex and higher performance electronic systems such as printed circuit boards and integrated circuits. Layout verification software, for example, is used to verify that a design of an IC chip conforms to certain manufacturing tolerances that are required in fabricating the chip, to ensure that the layout connectivity of the physical design of a chip matches the logical design of the chip represented by a schematic, and to model parasitic resistance and capacitance of the chip (known as “parasitic extraction”). These tools exist in one or more areas commonly referred to as electronic design automation (EDA), electronic computer aided design (ECAD), and technology computer aided design (TCAD). A single EDA platform can offer software modules for integrated circuit layout design, behavioral simulation, and functional analysis and verification.
For many EDA platforms, rules are specified in order to check the consistency between a physical design of a particular microchip, known as a “layout” in the art, and a logical design of that microchip, referred to as a “schematic.” In an operation, these rules are known as Layout Versus Schematic (LVS) rules. For some implementations, running a command file of LVS rules will extract devices and nets formed across the chip's layout hierarchy, and will then compare them to a schematic netlist for that chip to ensure that the layout connectivity of the physical design of a circuit matches the logical design of the circuit as defined by a schematic. In this regard, rule sets known as Layout Parasitic Extraction (LPE) rules are also specified to extract parasitic resistance and capacitance information from different sections of a chip. For a command file of LPE rules, the software platform will identify and simulate electromagnetic phenomena due to parasitic resistance and capacitance of the circuit.
As chip-interconnect and device-critical dimensions are reduced and, concomitantly, system frequency is increased, many additional parasitic effects must be considered and accounted for during system design, simulation and evaluation. Parasitic effects can cause inadvertent cross-coupling of signals, a reduction in signal voltage, and noise in signal, clock, and power distribution networks. If not properly accounted for during system design, there is an increased risk that the IC will experience functional failure or performance limitations following fabrication and implementation. Parasitics can radically degrade logic levels, delay clock and signal speeds, and otherwise prevent circuits from performing as designed. In general, shielding is not possible. The volume of parasitic effects has been increasing for each technology generation and, with increases in circuit size, complexity, and function, simulating the impact of these parasitics is an enormous challenge requiring very large computing resources and time.
Several tools and methodologies have been developed based on equivalent circuit extraction to allow for fast and accurate modeling of metallic interconnects belonging to a semiconductor layout. In such methodologies, the interconnect structures of the integrated circuit are divided into smaller sections, and each section is modeled by an equivalent circuit that models its electromagnetic behavior, including electrical behavior, along with any parasitic couplings to the substrate or other nearby structures. The aforementioned LPE methodologies are usually fast and efficient, and their output is usually a circuit netlist comprising R (resistor) and C (capacitor) lumped elements. Some methods are also capable of separately producing L (inductance) and K (mutual inductance) elements which, besides resistor and capacitor elements, are oftentimes required to accurately model the electromagnetic (EM) behavior of an IC at higher frequencies. There is a continuing need to improve these tools for each technology generation in order to address requirements for higher integration, greater functional capability and complexity, smaller chip area, and better performance of integrated circuits.